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this datasheet states saifun's current technical specifications regarding the products described herein. this datasheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 1907 rev: 1 amendment: 1 issue date: 10 september 2003 sa24c512 datasheet features ? = saifun nrom? nvm technology ? = operating voltage: 2.7v to 3.6v ? = clock frequency: 100/400/1700/3400 khz ? = low power consumption ? 0.5 a standby current typical (l version) ? <0.2 a standby current typical (lz version) ? = write modes ? byte mode ? page mode (128 bytes/page) ? = schmitt trigger inputs ? = hardware and software write protection for entire or partial array ? = endurance: up to 1 million data changes ? = data retention: greater than 40 years ? = packages: 8-pin dip, 8-pin soic and mlf leadless ? = temperature range ? commercial: 0c to +70c ? industrial (e): -40c to +85c 512kb eeprom iic http://www.saifun.com saifun nrom tm is a trademark of saifun semiconductors ltd.
sa24c512 datasheet saifun 2 general description sa24c512 is a 512-kbit cmos non- volatile serial eeprom organized as 64k x 8 bit memory. this device conforms to extended iic 2-wire protocol that allows accessing of memory in excess of 16kbit on an iic bus. this serial communication protocol uses a clock signal (scl) and a data signal (sda) to synchronously clock data between a master (e.g. a microcontroller) and a slave (eeprom). sa24c512 offers hardware write protection whereby the entire memory array can be write protected by pulling wp pin to logic high. the entire memory then becomes unalterable until the wp pin is switched to logic low. the device also features programmable write protect with options of full, half, or a quadrant of the array. the ?lz? version of the sa24c512 offers very low standby current, making it suitable for low-power applications. sa24c512 is designed to minimize pin count and simplify pc board layout requirements. this device is offered in so, dip and leadless mlf packages. saifun?s eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption.
sa24c512 datasheet saifun 3 table of contents features ......................................................................... 1 general description ...................................................... 2 block diagram ............................................................... 4 connection diagram ..................................................... 5 ordering information .................................................... 6 product specifications ................................................. 7 absolute maximum ratings operating conditions... 7 esd/latchup specification (jedec 8 spec) ........... 7 operating conditions............................................... 7 dc electrical characteristics (vcc 2.7v to 3.6v).... 8 capacitance ............................................................ 8 ac test conditions ................................................. 9 ac testing input/output waveforms....................... 9 ac characteristics (v cc 2.7v to 3.6v)..................... 9 bus timing ............................................................ 10 write cycle timing ................................................ 11 typical system configuration................................ 11 background information (iic bus) ............................. 12 slave address ....................................................... 12 device type .......................................................... 13 device/page block selection................................. 13 read/write bit....................................................... 13 acknowledge......................................................... 13 array address#1.................................................... 13 array address#0.................................................... 13 pin descriptions.......................................................... 14 serial clock (scl)................................................. 14 serial data (sda).................................................. 14 write protect (wp) ................................................ 14 choice 1: full array write protect ................. 14 choice 2: programmable write protect ......... 15 device selection inputs a1 and a0 (as appropriate)..................................................... 16 device operation......................................................... 17 clock and data conventions ................................. 17 start condition .................................................. 17 stop condition .................................................... 17 sa24c512 array addressing................................. 17 switching from f/s to hs mode and back............. 18 write operations ......................................................... 21 byte write ............................................................. 21 page write ............................................................ 21 acknowledge polling ............................................. 22 write protection .................................................... 22 read operations.......................................................... 23 current address read........................................... 23 random read ....................................................... 23 sequential read.................................................... 23 physical dimensions................................................... 25 contact information .................................................... 28 life support policy...................................................... 28 list of figures figure 1. sa24c512 block diagram................................ 4 figure 2. so, package (mw), dual-in-line package (n), top view ............................................................... 5 figure 3. leadless package (mlf), top view ................. 5 figure 4. sa24c512 ordering information ...................... 6 figure 5. ac testing input/output waveforms ................ 9 figure 6. bus timing ..................................................... 10 figure 7. write cycle timing ......................................... 11 figure 8. typical system configuration ......................... 11 figure 9 slave address ................................................. 12 figure 10. data transfer in hs-mode ............................ 18 figure 11. a complete hs-mode transfer ..................... 19 figure 12. data validity ................................................. 19 figure 13. start and stop definition ........................ 20 figure 14. acknowledge response from receiver ........ 20 figure 15. byte write .................................................... 22 figure 16. page write ................................................... 22 figure 17. current address read.................................. 24 figure 18. random read .............................................. 24 figure 19. sequential read........................................... 24 figure 20. 8-pin molded small outline package (mw) package number m08d ...................................... 25 figure 21. molded dual-in-line package (n) package number n08e...................................................... 26 figure 22. 8-pin mlf leadless package ....................... 27 list of tables table 1. pin names......................................................... 5
sa24c512 datasheet saifun 4 block diagram figure 1. sa24c512 block diagram
sa24c512 datasheet saifun 5 connection diagram sa24c512 1 2 3 4 8 7 6 5 a0 a1 nc v ss v cc wp scl sda figure 2. so, package (mw), dual-in-line package (n), top view sa24c512 1 2 3 4 8 7 6 5 a0 a1 nc v ss v cc scl sda figure 3. leadless package (mlf), top view note: for more details, see package number n08e and m08d. table 1. pin names pin name signal name description a0 device select address input has an internal "weak" pull down so that when left unconnected assumes logic low. a1 device select address input has an internal "weak" pull down so that when left unconnected assumes logic low. nc no connect v ss device ground input sda iic data input/output open collector/drain type scl iic clock input wp write protect has an internal "weak" pull down so that when left unconnected assumes logic low. when low, write is allowed to the memory array. when high, write is not allowed to the memory array as defined in write protect (wp) , page 14. v cc device power input 2.7 v to 3.6 v note: no a2 pin (pin 3) is provided. treated as no connect. internal address comparison assumes this pin to be 0 and hence the command code should have corresponding bit set to 0.
sa24c512 datasheet saifun 6 ordering information lz xx c 24 sa letter l lz 512 c 24 sa interface density voltage operating range description 2.7 v to 3.6 v 2.7 v to 3.6 v < 0.7 a standby current 512 kb with write protect cmos eeprom technology iic - 2 wire saifun non-volatile memory x blank x tube tape and reel pp package n mw mf 8-pin dip 8-pin soic (200 mil) 8-lead mlf f blank f non-lead free lead-free leads e blank e temp. range 0 to 70 c -40 to +85 c o o figure 4. sa24c512 ordering information
sa24c512 datasheet saifun 7 product specifications absolute maximum ratings operating conditions ambient storage temperature ?65 c to +150 c all input or output voltages with respect to ground 4.5 v to -0.3 v lead temperature (soldering, 10 seconds) +300 c esd rating 2000 v min. esd/latchup specification (jedec 8 spec) human body model minimum 2 kv machine model minimum 500 v latch up: 100 ma on all pins +125 c operating conditions ambient operating temperature sa24c512 sa24c512e 0 c to +70 c -40 c to +85 c
sa24c512 datasheet saifun 8 dc electrical characteristics (vcc 2.7v to 3.6v) limits symbol parameter test conditions min typ (notes) max units f scl = 100 khz (read) 2 3 ma f scl = 100 khz (write) 8 11 ma f scl = 400 khz (read) 2 3 ma f scl = 400 khz (write) 8 11 ma f scl = 1.7 mhz (read) 5 7 ma f scl = 1.7 mhz (write) 8 11 ma f scl = 3.4 mhz (read) 5 7 ma i cca active power supply current f scl = 3.4 mhz (write) 8 11 ma i sb standby current (l) v in = gnd or v cc 0.5 1 a standby current (lz) v in = gnd or v cc 0.2 0.7 a = i il input leakage current v in = gnd to v cc 0.1 1 a i ol output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage -0.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 3 ma 0.4 v notes (1) typical values are ta = 25 c and nominal supply voltage of 3 volts. (2) write frequency is 50 hz. capacitance t a = +25 c, f = 100/400 khz/1.7 mhz/3.4 mhz, v cc = 3v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf notes: (1) this parameter is periodically sampled and not 100% tested. (2) typical values are t a = 25 c and nominal supply voltage of 3 volts.
sa24c512 datasheet saifun 9 ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.3 to v cc x 0.7 output load 1 ttl gate and c l = 100 pf ac testing input/output waveforms figure 5. ac testing input/output waveforms ac characteristics (v cc 2.7v to 3.6v) 100 khz 400 khz 1.7 mhz 3.4 mhz symbol parameter min max min max min max min max units f scl scl clock frequency 100 400 1700 3400 khz t low clock low period 4700 1300 320 160 ns t high clock high period 4000 600 120 60 ns tsu:sta start condition setup time (for a repeated start condition) 4700 600 160 160 ns t hd:sta start condition hold time (for a repeated start condition) 4000 600 160 160 ns t su:sto stop condition setup time 4000 600 160 160 ns t rda sda rise time (depend on external pull-up) 1000 300 20 170 10 85 ns t fda sda fall time 300 300 20 170 10 85 ns t rcl scl rise time (depend on external pull-up) 1000 300 20 80 10 40 ns t fcl scl fall time 300 300 20 80 10 40 ns t rcl1 scl rise time after repeated start or after ack bit na na na 20 160 10 80 ns t su:dat data in setup time 250 100 20 20 ns t hd:dat data in hold time 0 0 0 0 ns t dh data out hold time 300 100 0 0 ns
sa24c512 datasheet saifun 10 100 khz 400 khz 1.7 mhz 3.4 mhz symbol parameter min max min max min max min max units t i noise suppression time constant at scl, sda inputs (minimum v in pulse width) 50 50 10 10 ns t aa scl low to sda data out valid 300 1 3500 100 1 900 0 170 0 85 ns t buf time the bus must be free before a new transmission can start 4700 1300 320 160 ns t wr write cycle time 10 10 10 10 ms endurance 1 million 2 cycles 1 the minimum value is defined to bridge the undefined part between v ih and v il of the falling edge of scl. the standard number is 0 ns. 2 this parameter is not tested but ensured by characterization. bus timing figure 6. bus timing
sa24c512 datasheet saifun 11 write cycle timing figure 7. write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. typical system configuration figure 8. typical system configuration note: due to the open-drain configuration of sda and scl, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ).
sa24c512 datasheet saifun 12 background information (iic bus) extended iic specification is an extension of the standard iic specification, which enables addressing of eeproms with more than 15 kbits of memory on an iic bus. the difference between the two specifications is that the extended iic specification defines two bytes of "array address" information, while the standard iic specification defines only one. all other aspects are identical between the two specifications. using two bytes of array address and two address signals (a1 and a0), it is now possible to address up to 4 mbits (2 8 2 8 2 2 8 = 2 mbits) of memory on an iic bus. note that due to format difference, it is not possible to have both peripherals that follow the standard iic specification (e.g., 16-kbit eeprom) and peripherals that follow the extended iic specification (e.g., 512-kbit eeprom) on a common iic bus. the iic bus allows synchronous bidirectional communication between a transmitter and a receiver using a clock signal (scl) and a data signal (sda). additionally, there are two address signals (a1 and a0) that collectively serve as a "chip select signal" to a device (e.g., eeprom) on the bus. all communication on the iic bus must be started with a valid start condition by a master, followed by transmittal by the master of byte(s) of information (address/data). for every byte of information received, the addressed receiver provides a valid acknowledge pulse to further continue the communication unless the receiver intends to discontinue the communication. depending on the direction of transfer (write or read), the receiver can be either a slave or the master. a typical iic communication concludes with a stop condition (by the master). addressing an eeprom memory location involves sending a command string with the following information: [device type]?[device/page block selection]?[r/w bit]?[array address#1]?[array address#0] slave address the slave address is an 8-bit information consisting of a device type field (4 bits), device/page block selection field (3 bits) and read/write bit (1 bit). figure 9 slave address
sa24c512 datasheet saifun 13 device type the iic bus is designed to support a variety of devices, such as rams, eproms, and so on., along with eeproms. to properly identify various devices on the iic bus, a 4-bit ?device type? identifier string is used. for eeproms, this 4-bit string is 1-0-1-0. every iic device on the bus internally compares this 4-bit string to its own ?device type? string to ensure proper device selection. device/page block selection when multiple devices of the same type (e.g., multiple eeproms) are present on the iic bus, the a1 and a0 address information bits are used in device selection. every iic device on the bus internally compares this 3-bit string to its own physical configuration (a1 and a0 pins) to ensure proper device selection. this comparison is in addition to the ?device type? comparison. in addition to selecting an eeprom, these 3 bits are also used to select a ?page block? within the selected eeprom. each page block is 512 kbits (64 kbytes) in size. if an eeprom contains more than one page block, the selection of a page block within the eeprom is by using a1 and a0 bits. read/write bit last bit of the slave address indicates if the intended access is read or write. if the bit is 1, the access is read; if it is 0, the access is write. acknowledge acknowledge is an active low pulse on the sda line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8 bits of data. the receiver provides an ack pulse for every 8 bits of data received. this handshake mechanism is done as follows: after transmitting 8 bits of data, the transmitter releases the sda line and waits for the ack pulse. the addressed receiver, if present, drives the ack pulse on the sda line during the ninth clock and releases the sda line back (to the transmitter). refer to figure 14. array address#1 this is an 8-bit information containing the most significant 8 bits of the 16-bit memory array address of a location to be selected within a page block of the device. array address#0 this is an 8-bit information containing the least significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device.
sa24c512 datasheet saifun 14 pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire?ored with any number of open drain or open collector outputs. write protect (wp) choice 1: full array write protect if pulled high, write operations will not be executed. read operations are possible. if pulled low, normal operation is enabled, read/write over the entire memory is possible. this feature allows the user to assign the entire memory as rom, which can be protected against accidental programming. when write is disabled, the slave address and word address will be acknowledged but data will not be acknowledged. this pin has an internal pull-down circuit. however, on systems where write protection is not required it is recommended that this pin be tied to v ss . write protection truth table wp pin "less than" comparison t/b bit write allowed 1 yes 0 no 1 no 0 yes 1 yes 1 yes 1 no 1 no 0 don't care don't care yes
sa24c512 datasheet saifun 15 choice 2: programmable write protect (1) the programmable write protection is available to customers by contacting a sales representative. an internal 8-bit wide internal nv-latch is used, with the following definition: 1 predefined on sort. not a user command. example (512k ) write protection area nv-latch bit setting - bits [7:0] result 1 full array (0x0000 - 0xffff) x-0-0-0-0-0-0-1 address bits (a15:a10) issued during the write command are compared against bits[6:0] of this nv-latch. since bit[0] of this nv-latch is set to 1, write is not allowed as long as the comparison results in "greater than or equal to" status. 2 bottom half (0x0000 - 0x7fff) x-1-0-0-0-0-0-0 same as example 1. 3 bottom quadrant (0x0000 - 0x3fff) x-0-1-0-0-0-0-0 same as example 1. 4 top quadrant (0xfff - oxc000) x-1-1-0-0-0-0-1 address bits (a15:a10) issued during the write command are compared against bits[6:0] of this nv-latch. since bit[0] of this nv-latch is set to 1, write is allowed as long as the comparison results in "greater than or equal to" status. 5 top half (0xfff - 0x8000) x-1-0-0-0-0-0-1 same as example 4. 6 no write protection x-0-0-0-0-0-0-0 same as example 4.
sa24c512 datasheet saifun 16 device selection inputs a1 and a0 (as appropriate) these inputs collectively serve as a ?chip select? signal to an eeprom when multiple eeproms are present on the same iic bus. hence these inputs, if present, should be connected to either v cc or v ss in a unique manner to enable proper selection of an eeprom among multiple eeproms. during a typical addressing sequence, every eeprom on the iic bus compares the configuration of these inputs to the respective 3-bit ?device/page block selection? information (part of the slave address) to determine a valid selection. for example, if the 3-bit ?device/page block selection? is 1-0-1, the eeprom whose ?device selection inputs? (a1 and a0) are connected to v cc -v ss -v cc , respectively, is selected. only a1 and a0 are provided on the sa24c512, which means that the corresponding a2 bit in the "device/page block selection" should be set to 0 during all access to the device. these two pins have a weak internal pull-down circuit.
sa24c512 datasheet saifun 17 device operation the sa24c512 supports a bidirectional bus-oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the sa24c512 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figure 12. start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the sa24c512 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. refer to figure 13. stop condition all communications are terminated by a stop condition, which is a low-to-high transition of sda when scl is high. the stop condition is also used by the sa24c512 to place the device in the standby power mode. refer to figure 13. sa24c512 array addressing during read/write operations, addressing the eeprom memory array involves in providing two address bytes, "word address 1" and "word address 0." the "word address 1" byte contains the eight most significant bits of the array address, while "word address 0" byte contains the eight least significant bits of the array address.
sa24c512 datasheet saifun 18 switching from f/s to hs mode and back after reset and initialization, the device must be in fast mode. the master on the bus can choose to switch the connected slave devices to hs mode. the slave device must then recognize the "s 00001xxx a" sequence and switch its internal circuit from fast mode to hs mode. each device must recognize the stop condition and switch back to fast mode timings and flow are shown in the figures below. figure 10. data transfer in hs-mode
sa24c512 datasheet saifun 19 figure 11. a complete hs-mode transfer figure 12. data validity
sa24c512 datasheet saifun 20 figure 13. start and stop definition figure 14. acknowledge response from receiver
sa24c512 datasheet saifun 21 write operations byte write two bytes of address are required after the slave address for a byte write operation. these two bytes select one out of the 64k locations in the memory. the master provides these two address bytes and for each address byte received, sa24c512 responds with an acknowledge pulse. the master then provides a byte of data to be written into the memory. upon receipt of this data, the sa24c512 responds with an acknowledge pulse. the master then terminates the transfer by generating a stop condition, at which time the sa24c512 begins the internal write cycle to the memory. while the internal write cycle is in progress, the sa24c512 inputs are disabled, and the device will not respond to any requests from the master for the duration of t wr . refer to figure 15 for the address, acknowledge and data transfer sequence. page write to minimize write cycle time, the sa24c512 offers a page write feature, which allows simultaneous programming of up to 128 contiguous bytes. to facilitate this feature, the memory array is organized in terms of ?pages.? a page consists of 128 contiguous byte locations starting at every 128-byte address boundary (for example, starting at array address 0x0000, 0x0080, 0x0100, and so on). the page write operation is confined to a single page, which means that it will not cross over to locations on the next page but instead ?rolls over? to the beginning of the page whenever the end of a page is reached and additional data bytes continue to be provided. a page write operation can be initiated to begin at any location within a page (the starting address of the page write operation need not be the starting address of a page). page write is initiated in the same manner as the byte write operation, but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 127 more bytes. after the receipt of each byte, the sa24c512 will respond with an acknowledge pulse, increment the internal address counter to the next address, and becomes ready to accept the next data. if the master should transmit more than 128 bytes prior to generating the stop condition, the address counter will ?roll over? and previously loaded data will be re-loaded. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 16 for the address, acknowledge, and data transfer sequence.
sa24c512 datasheet saifun 22 acknowledge polling once the stop condition is issued to indicate the end of the host?s write operation, the sa24c512 initiates the internal write cycle. ack polling can be initiated immediately, which involves issuing the start condition followed by the slave address for a write operation. if the sa24c512 is still busy with the write operation, no ack will be returned. if the sa24c512 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection programming the memory will not take place if the wp pin of the sa24c512 is pulled high. the sa24c512 will respond to the slave and byte addresses, but will not generate an acknowledge after the first byte of data has been received. thus, the program cycle will not be started when the stop condition is asserted. figure 15. byte write figure 16. page write
sa24c512 datasheet saifun 23 read operations read operations are initiated in the same manner as write operations, with the exception that the r/ w bit of the slave address is set to 1. there are three basic read operations: current address read, random read and sequential read. current address read internally, the sa24c512 contains an address counter that maintains the address of the last byte accessed, incremented by 1. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/ w set to 1, the sa24c512 issues an acknowledge and transmits the 8-bit word. the master will not acknowledge the transfer but does generate a stop condition, and therefore the sa24c512 discontinues transmission. refer to figure 17 for the address, acknowledge and data transfer sequence. random read random read operations enable the master to access any memory location in a random manner. prior to issuing the slave address with the r/ w bit set to 1, the master must first perform a ?dummy? write operation. the master issues the start condition, the slave address with the r/ w bit set to 0 and then the byte address is read. after the byte address is acknowledged, the master immediately issues another start condition and the slave address with the r/ w bit set to 1. this will be followed by an acknowledge from the sa24c512 and then by the 8-bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the sa24c512 discontinues transmission. refer to figure 18 for the address, acknowledge, and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the sa24c512 continues to output data for each acknowledge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. the data output is sequential with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" to the beginning of the memory. the sa24c512 continues to output data for each acknowledge received. refer to figure 19 for the address, acknowledge, and data transfer sequence.
sa24c512 datasheet saifun 24 figure 17. current address read figure 18. random read figure 19. sequential read
sa24c512 datasheet saifun 25 physical dimensions all measurements are in inches (millimeters), unless otherwise specified. figure 20. 8-pin molded small outline package (mw) package number m08d
sa24c512 datasheet saifun 26 figure 21. molded dual-in-line package (n) package number n08e
sa24c512 datasheet saifun 27 figure 22. 8-pin mlf leadless package
sa24c512 datasheet saifun 28 contact information international headquarters united states saifun semiconductors ltd. elrod building 45 hamelach st. sappir industrial park netanya 42504 israel tel.: +972-9-892-8444 fax: +972-9-892-8445 saifun semiconductors inc. 2350 mission college blvd. suite 1070 santa clara, ca 95054 u.s.a. tel: +1-408-982-5888 fax: +1-408-982-5890 email: tech_support@saifun.com http://www.saifun.com revision history rev. date description of change 0.0 5 sept 2002 initial release 1.0 4-aug-2003 added mlf package and minor format improvements 1.1 10-sept 2003 changed endurance to 1 million cycles ? saifun semiconductors ltd. 2003 saifun reserves the right, without notice, to change any of the products described in this guide, in order to improve functiona lity, reliability or design. saifun assumes no liability arising from the application or use of any product described in this guide; and under its patent rights, gives no authorization for the use of this product or associated products. saifun makes no warranty fo r use of its products, other than expressly provided by saifun in any applicable warranty. the buyer will not hold saifun responsible for direct or indirect damages and expenses, as well as any claim of injury or death, associated with the unauthorized use, includi ng claims of manufacture or design negligence. saifun and saifun nrom are trademarks or registered trademarks of saifun semiconductors ltd. other company and brand products and service names are trademarks or registered trademarks of their respective holders. life support policy saifun's products are not authorized for use as critical components in life support devices or systems without the express writ ten approval of the president of saifun semiconductors ltd. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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